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Three-dimensional (3D) integration is pointed out as a potential road for non-stop functionality development in built-in circuits (IC) because the traditional scaling procedure is confronted with exceptional demanding situations in basic and financial limits. Wafer point 3D IC can take a number of kinds, they usually often comprise a stack of numerous thinned IC layers which are vertically bonded and interconnected by means of via silicon through TSV.

There is a protracted string of advantages that it is easy to derive from 3D IC implementation comparable to shape issue, density multiplication, better hold up and gear, more desirable bandwidth, and heterogeneous integration. This ebook offers contributions by way of key researchers during this box, masking motivations, expertise structures, purposes, and different layout matters.

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The 3D-IC approach using TSV interconnects, which provides electrical pathways through the thickness of a Si die, calls for a combination of via processes, extreme wafer thinning, and various wafer-to-wafer and chipto-wafer bonding techniques with thin wafer handling mechanisms. There are various factors related to device integration, which should be considered before adopting TSV technology design. Those include (a) TSV process flow type: via-first, via-middle or via-last, (b) bonding process type: chip-to-chip, chip-to-wafer or wafer-to-wafer, (c) substrates stacking approach: face-toback or face-to-face, (d) using or not using interposer, (e) substrate type: bulk silicon wafer or silicon-on-insulator (SOI) wafer, and so on.

On the face of it, making a 3D system sounds like a panacea. It solves the evolutionary problem of continuing to scale the number of transistors in a chip, known as Moore’s law. It seems to be a no brainer. The goal of this chapter is to bring some perspectives to this initial reaction. Building a system in 3D does enable a few specific opportunities. It also requires solving some completely new sets of problems. As will become clearer in this chapter, you should first decide what problems need to be solved by building a system in 3D before figuring out how to go about building it.

M. Lu, “Low temperature copper-nanorod bonding for 3D integration,” Materials Research Society Symposium Proceedings, 970, pp. 225-230, 2007. 39. P. Benkart, A. Kaiser, A. Munding, M. -J. Pfleiderer, E.  Heittmann, and U. Ramacher, “3D chip stack technology using through-chip interconnects,” IEEE Design & Test of Computers, 22(6), pp. 512-518, 2005. 40. P. Gueguen, L. Di Cioccio, M. Rivoire, D. Scevola, M. Zussy, A. M. Charvet, L. Bally, and L. Clavelier, “Copper direct bonding for 3D integration,” IEEE International Interconnect Technology Conference, pp.

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